Synthesizable 2D Vernier TDC based on gated ring oscillators

Abstract

Time to digital converter (TDC) is a device, which measures time interval between two edges of signals and converts it to digital code. Lately it is used as phase detector in all-digital frequency synthesizers. One of main parameters of TDC is resolution, which describes smallest time interval, which can be measured using TDC. Resolution of basic inverter-based TDC improves with reduction of delay of inverter in modern nanometric CMOS technology nodes. But in more mature technologies delay of inverter does not provide needed TDC resolution. In this paper sub-inverter-resolution 2D Vernier TDC, which is based on gated ring oscillators and is implemented in VHDL hardware description language for easy migration to various technology nodes, is presented. It is synthesized, placed and routed in 65 nm CMOS technology. Main blocks of TDC are two gated ring oscillators, their lap and edge counters, arbiter matrix, output decoder and control block. Frequency and single stage delay of gated ring oscillators is changed by switching parallelconnected sections of three-stage oscillators. Tuning step of single stage delay of gated ring oscillator, which is equal to the resolution of TDC, can be changed from 3.2 to 0.8 ps at typical operation conditions, when number of enabled stages of oscillator is changed from 22 to 48. TDC occupies 123,0 µm × 148,8 µm area of silicon.

Časovno digitalni pretvorniki (TDC) so naprave, ki merijo časovni interval med dvema roboma signal in ga pretvorijo v digitalno obliko. Pretvornik je uporabljen kot fazni detektor v digitalnih frekvenčnih sintetizatorjih. Glavni parameter TDC je resolucija, kije opisana kot najmanjši časovni interval, ki ga še lahko izmeri. Resolucija osnovnih invertirajočih TDC se izboljša z znižanjem zakasnitev inverterja v moderni nanometrski CMOS tehnologiji. Pri zrelih tehnologijah zakasnitev ne omogoča doseganja željene resolucije TDC. V članku je predstavljen 2D Vernier TDC na osnovi obročnega oscilatorja s podinvertersko resolucijo. Zaradi lažje migracije v različne tehnologije je realiziran v VHDL strojnem jeziku. Sestavljen je v 65 nm CMOS tehnologiji. Glavni bloki TDC so: dva krožna oscilatorja na osnovi vrat, njihov krog, robni števci, arbitna matrika, izhodni dekoder in kontrolni blok. Frekvenčne in enostanjske zakasnitve se spreminjajo s preklapljanjem vzporedno vezanih sekcij tristanjskega oscilatorja. Korak je nastavljiv od 3.2 do 0.8 ps pri tipičnem delovanju in predstavlja resolucijo TDC. Velikost TDCja je 123,0 μm × 148,8 μm.