| dc.contributor.author | Navickas, Romualdas | |
| dc.contributor.author | Čiulada, Rimas | |
| dc.date.accessioned | 2023-09-18T18:53:00Z | |
| dc.date.available | 2023-09-18T18:53:00Z | |
| dc.date.issued | 2002 | |
| dc.identifier.issn | 1392-124X | |
| dc.identifier.other | (BIS)VGT02-000005063 | |
| dc.identifier.uri | https://etalpykla.vilniustech.lt/handle/123456789/132667 | |
| dc.description.abstract | A model of the evolution of masks in the process of underetching (lateral etching) layers is created for analysis and design of new technologies semiconductor devices and integrated circuits. The results of the simulation are given for different configurations, speeds and etching selectivity of masks. | eng |
| dc.format.extent | p. 65-68 | |
| dc.format.medium | tekstas / txt | |
| dc.language.iso | eng | |
| dc.title | Design of the masks for the self-alignment technologies of integrated circuits | |
| dc.type | Straipsnis kitame recenzuotame leidinyje / Article in other peer-reviewed source | |
| dc.type.pubtype | S4 - Straipsnis kitame recenzuotame leidinyje / Article in other peer-reviewed publication | |
| dc.contributor.institution | Vilniaus Gedimino technikos universitetas | |
| dc.contributor.faculty | Elektronikos fakultetas / Faculty of Electronics | |
| dc.subject.researchfield | T 001 - Elektros ir elektronikos inžinerija / Electrical and electronic engineering | |
| dcterms.sourcetitle | Informacinės technologijos ir valdymas | |
| dc.description.issue | nr. 4(25) | |
| dc.publisher.name | Technologija | |
| dc.publisher.city | Kaunas | |
| dc.identifier.elaba | 3619839 | |
