| dc.contributor.author | Pomarnacki, Raimondas | |
| dc.contributor.author | Gurskas, Antanas | |
| dc.contributor.author | Urbanavičius, Vytautas | |
| dc.date.accessioned | 2023-09-18T19:17:39Z | |
| dc.date.available | 2023-09-18T19:17:39Z | |
| dc.date.issued | 2012 | |
| dc.identifier.issn | 1392-1215 | |
| dc.identifier.other | (BIS)VGT02-000025190 | |
| dc.identifier.uri | https://etalpykla.vilniustech.lt/handle/123456789/137534 | |
| dc.description.abstract | The algorithm for synthesis of the multi-tapped meander delay line (MTMDL) topology is proposed in this article. The algorithm is based on search of construction parameters of the MTMDL according to Monte Carlo method. Proposed algorithm was realized as software and tested on 14 nodes computer cluster. Experimental synthesis of lines has shown adequacy of the suggested algorithm. It has been shown that increasing number of nodes in the cluster, synthesis is executing faster and parallel part of the algorithm approaches to 90 percent of total algorithm. It is revealed that the maximal efficiency of the algorithm is achieved when the number of cluster nodes reaches the number of all issued synthesis processes. | eng |
| dc.format | PDF | |
| dc.format.extent | p. 41-44 | |
| dc.format.medium | tekstas / txt | |
| dc.language.iso | eng | |
| dc.relation.isreferencedby | Science Citation Index Expanded (Web of Science) | |
| dc.relation.isreferencedby | INSPEC | |
| dc.relation.isreferencedby | VINITI | |
| dc.source.uri | https://doi.org/10.5755/j01.eee.18.8.2608 | |
| dc.title | Topology synthesis of the Multi-Tapped Meander Delay Line using Monte Carlo method | |
| dc.type | Straipsnis Web of Science DB / Article in Web of Science DB | |
| dcterms.references | 13 | |
| dc.type.pubtype | S1 - Straipsnis Web of Science DB / Web of Science DB article | |
| dc.contributor.institution | Vilniaus Gedimino technikos universitetas | |
| dc.contributor.faculty | Elektronikos fakultetas / Faculty of Electronics | |
| dc.subject.researchfield | T 001 - Elektros ir elektronikos inžinerija / Electrical and electronic engineering | |
| dc.subject.en | Circuit topology | |
| dc.subject.en | Delay lines | |
| dc.subject.en | Integrated circuit synthesis | |
| dc.subject.en | Microwave devices | |
| dc.subject.en | Parallel algorithms | |
| dcterms.sourcetitle | Elektronika ir elektrotechnika | |
| dc.description.issue | no. 8 | |
| dc.description.volume | Vol. 18 | |
| dc.publisher.name | KTU | |
| dc.publisher.city | Kaunas | |
| dc.identifier.doi | 000310422400009 | |
| dc.identifier.doi | 10.5755/j01.eee.18.8.2608 | |
| dc.identifier.elaba | 3995009 | |