| dc.contributor.author | Pomarnacki, Raimondas | |
| dc.contributor.author | Urbanavičius, Vytautas | |
| dc.date.accessioned | 2023-09-18T19:52:58Z | |
| dc.date.available | 2023-09-18T19:52:58Z | |
| dc.date.issued | 2013 | |
| dc.identifier.issn | 1392-1215 | |
| dc.identifier.other | (BIS)VGT02-000027033 | |
| dc.identifier.uri | https://etalpykla.vilniustech.lt/handle/123456789/144324 | |
| dc.description.abstract | An algorithm, based on the successive approximation technique for the parallel synthesis of the multi-tapped meander microstrip delay line (MTMDL), is presented. Multiconductor line model and finite difference method are used for analysis of the MTMDL. Parallel computations in the proposed algorithm are organized according to both – data parallelism and task parallelism concepts. Efficiency of two parallel synthesis algorithms one proposed, and another based on Monte Carlo method, is compared. It is shown that while number of computational nodes is small by comparison (e.g. not larger than 3) then efficiency of the proposed algorithm about 5 times exceeds Monte Carlo method based algorithm efficiency. It is revealed that efficiency of both algorithms becomes similar when computational nodes number increases several times. | eng |
| dc.format | PDF | |
| dc.format.extent | p. 72-75 | |
| dc.format.medium | tekstas / txt | |
| dc.language.iso | eng | |
| dc.relation.isreferencedby | Science Citation Index Expanded (Web of Science) | |
| dc.relation.isreferencedby | INSPEC | |
| dc.relation.isreferencedby | VINITI | |
| dc.source.uri | http://dx.doi.org/10.5755/j01.eee.19.7.5166 | |
| dc.title | Parallel algorithms for the synthesis of the multi-tapped meander delay lines | |
| dc.type | Straipsnis Web of Science DB / Article in Web of Science DB | |
| dcterms.references | 11 | |
| dc.type.pubtype | S1 - Straipsnis Web of Science DB / Web of Science DB article | |
| dc.contributor.institution | Vilniaus Gedimino technikos universitetas | |
| dc.contributor.faculty | Elektronikos fakultetas / Faculty of Electronics | |
| dc.subject.researchfield | T 001 - Elektros ir elektronikos inžinerija / Electrical and electronic engineering | |
| dc.subject.en | Circuit topology | |
| dc.subject.en | Delay lines | |
| dc.subject.en | Integrated circuit synthesis | |
| dc.subject.en | Microwave devices | |
| dc.subject.en | Parallel algorithms | |
| dcterms.sourcetitle | Elektronika ir elektrotechnika | |
| dc.description.issue | no.7 | |
| dc.description.volume | Vol. 19 | |
| dc.publisher.name | KTU | |
| dc.publisher.city | Kaunas | |
| dc.identifier.doi | 000324641600015 | |
| dc.identifier.doi | 10.5755/j01.eee.19.7.5166 | |
| dc.identifier.elaba | 4039182 | |