dc.contributor.author | Kulakovskis, Darius | |
dc.contributor.author | Sledevič, Tomyslav | |
dc.contributor.author | Gedminas, Aurimas | |
dc.contributor.author | Navakauskas, Dalius | |
dc.date.accessioned | 2023-09-18T16:52:41Z | |
dc.date.available | 2023-09-18T16:52:41Z | |
dc.date.issued | 2016 | |
dc.identifier.other | (BIS)VGT02-000033421 | |
dc.identifier.uri | https://etalpykla.vilniustech.lt/handle/123456789/117457 | |
dc.description.abstract | Metabolic P (MP) system formalism is already proven to be applicable and useful in various fields of science, however knowledge about possibilities of MP system implementation in a hardware is limited. The use of a reconfigurable hardware empowers investigation in a search of the best implementation strategy for specified computing. Thus in the paper FPGA implementation techniques for MP systems were examined and compared. The MP system that models the process of Glucose-Insulin interactions in the intravenous glucose tolerance test was used in the study. It was implemented in FPGA by the use of three alternative FPGA implementation techniques: single process, single DSP slice and pipelined implementation. Experimental results together with suggested evaluation metrics were estimated. It was shown that single DSP slice implementation is preferable if minimal FPGA resource utilization is required, while pipelined technique use yields MP system that has a better balance between operating frequency and latency. | eng |
dc.format | PDF | |
dc.format.extent | p. 1-5 | |
dc.format.medium | tekstas / txt | |
dc.language.iso | eng | |
dc.relation.isreferencedby | Conference Proceedings Citation Index - Science (Web of Science) | |
dc.relation.isreferencedby | IEEE Xplore | |
dc.source.uri | http://ieeexplore.ieee.org/document/7821816/ | |
dc.subject | IK04 - Skaitmeninės signalų apdorojimo technologijos / Digital signal processing technologies | |
dc.title | Alternative implementations of metabolic P system in FPGA | |
dc.type | Straipsnis konferencijos darbų leidinyje Web of Science DB / Paper in conference publication in Web of Science DB | |
dcterms.accessRights | organized by: Vilnius Gediminas Technical University, Riga Technical University, IEEE Latvia Section | |
dcterms.references | 22 | |
dc.type.pubtype | P1a - Straipsnis konferencijos darbų leidinyje Web of Science DB / Article in conference proceedings Web of Science DB | |
dc.contributor.institution | Vilniaus Gedimino technikos universitetas | |
dc.contributor.faculty | Elektronikos fakultetas / Faculty of Electronics | |
dc.subject.researchfield | N 009 - Informatika / Computer science | |
dc.subject.researchfield | T 001 - Elektros ir elektronikos inžinerija / Electrical and electronic engineering | |
dc.subject.ltspecializations | L106 - Transportas, logistika ir informacinės ir ryšių technologijos (IRT) / Transport, logistic and information and communication technologies | |
dc.subject.en | Field programmable gate arrays | |
dc.subject.en | Biological system modeling | |
dc.subject.en | Digital signal processors | |
dcterms.sourcetitle | AIEEE’2016 : 2016 IEEE 4th workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE) : proceedings of the 4th IEEE workshop, November 10–12, 2016 Vilnius, Lithuania / edited by: Dalius Navakauskas, Andrejs Romanovs, Darius Plonis | |
dc.publisher.name | IEEE | |
dc.publisher.city | Washington | |
dc.identifier.doi | 000393578900016 | |
dc.identifier.doi | 10.1109/AIEEE.2016.7821816 | |
dc.identifier.elaba | 20278972 | |