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dc.contributor.authorKulakovskis, Darius
dc.contributor.authorSledevič, Tomyslav
dc.contributor.authorGedminas, Aurimas
dc.contributor.authorNavakauskas, Dalius
dc.date.accessioned2023-09-18T16:52:41Z
dc.date.available2023-09-18T16:52:41Z
dc.date.issued2016
dc.identifier.other(BIS)VGT02-000033421
dc.identifier.urihttps://etalpykla.vilniustech.lt/handle/123456789/117457
dc.description.abstractMetabolic P (MP) system formalism is already proven to be applicable and useful in various fields of science, however knowledge about possibilities of MP system implementation in a hardware is limited. The use of a reconfigurable hardware empowers investigation in a search of the best implementation strategy for specified computing. Thus in the paper FPGA implementation techniques for MP systems were examined and compared. The MP system that models the process of Glucose-Insulin interactions in the intravenous glucose tolerance test was used in the study. It was implemented in FPGA by the use of three alternative FPGA implementation techniques: single process, single DSP slice and pipelined implementation. Experimental results together with suggested evaluation metrics were estimated. It was shown that single DSP slice implementation is preferable if minimal FPGA resource utilization is required, while pipelined technique use yields MP system that has a better balance between operating frequency and latency.eng
dc.formatPDF
dc.format.extentp. 1-5
dc.format.mediumtekstas / txt
dc.language.isoeng
dc.relation.isreferencedbyConference Proceedings Citation Index - Science (Web of Science)
dc.relation.isreferencedbyIEEE Xplore
dc.source.urihttp://ieeexplore.ieee.org/document/7821816/
dc.subjectIK04 - Skaitmeninės signalų apdorojimo technologijos / Digital signal processing technologies
dc.titleAlternative implementations of metabolic P system in FPGA
dc.typeStraipsnis konferencijos darbų leidinyje Web of Science DB / Paper in conference publication in Web of Science DB
dcterms.accessRightsorganized by: Vilnius Gediminas Technical University, Riga Technical University, IEEE Latvia Section
dcterms.references22
dc.type.pubtypeP1a - Straipsnis konferencijos darbų leidinyje Web of Science DB / Article in conference proceedings Web of Science DB
dc.contributor.institutionVilniaus Gedimino technikos universitetas
dc.contributor.facultyElektronikos fakultetas / Faculty of Electronics
dc.subject.researchfieldN 009 - Informatika / Computer science
dc.subject.researchfieldT 001 - Elektros ir elektronikos inžinerija / Electrical and electronic engineering
dc.subject.ltspecializationsL106 - Transportas, logistika ir informacinės ir ryšių technologijos (IRT) / Transport, logistic and information and communication technologies
dc.subject.enField programmable gate arrays
dc.subject.enBiological system modeling
dc.subject.enDigital signal processors
dcterms.sourcetitleAIEEE’2016 : 2016 IEEE 4th workshop on Advances in Information, Electronic and Electrical Engineering (AIEEE) : proceedings of the 4th IEEE workshop, November 10–12, 2016 Vilnius, Lithuania / edited by: Dalius Navakauskas, Andrejs Romanovs, Darius Plonis
dc.publisher.nameIEEE
dc.publisher.cityWashington
dc.identifier.doi000393578900016
dc.identifier.doi10.1109/AIEEE.2016.7821816
dc.identifier.elaba20278972


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