Digital signal processing algorithm for measurement of settling time of high-resolution high-speed DACs
Date
2019Author
Kvedaras, Rokas
Kvedaras, Vygaudas
Ustinavičius, Tomas
Masiulionis, Ričardas
Metadata
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The paper presents the developed complex Digital Signal Processing algorithm for the reduction of white and 1/f noise and processing of the measurement signals of the Settling Time Measurement of the Digital-to-Analog Converters. The results show that the proposed DSP algorithm ensures 100-fold suppression of the white noise and 1/f noise. It was shown that it is possible to measure settling times of highspeed DACs (up to 16-17 Bits) with readout levels of ± 0.5 LSB while measurement errors do no exceed ± 1.4 ns.