Acceleration of feature extraction for FPGA-based speech recognition

Abstract

The paper describes a field programmable gate array implementation of the main part of speech recognition system - feature extraction. In order to accelerate recognition the whole cepstral analysis scheme is implemented in hardware by the use of intellectual property cores. Two field programmable gate array devices are used for evaluation. Comparative experimental results of four different implementations are presented. They grounds achieved 29 times faster speech analysis in comparison with software based analysis subsystem.