Phase noise minimization in CMOS voltage controlled oscillators

Abstract

Relaxation RC type voltage controlled oscillator is more desirable for many applications because of wide frequency generation range, small size on chip and linear voltage to frequency transfer characteristic. The limiting factor of such voltage controlled oscillator type is that it has higher phase noise in comparison with liquid crystal oscillators. We discuss how different device components, parameters and configuration influence phase noise, including transistor noise sources dependence on its geometrical parameters. The simulation results of the relaxation voltage controlled oscillator which was implemented in different 180 nm and 90 nm CMOS technologies are reported.