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dc.contributor.authorBaškys, Algirdas
dc.date.accessioned2023-09-18T19:08:17Z
dc.date.available2023-09-18T19:08:17Z
dc.date.issued2010
dc.identifier.issn1736-3705
dc.identifier.other(BIS)VGT02-000024598
dc.identifier.urihttps://etalpykla.vilniustech.lt/handle/123456789/135861
dc.description.abstractThe input offset voltage of the differential amplifier based on the bipolar junction transistors, which operate at high current density, is analysed in this work. An analytical approach based on the equations in the explicit form is used to determine the input offset voltage reduction means. The obtained results are tested using numerical simulation of the differential amplifier.eng
dc.format.extentp. 103-106
dc.format.mediumtekstas / txt
dc.language.isoeng
dc.relation.isreferencedbyIEEE Xplore
dc.titleThe means of the differential amplifier input offset voltage reduction
dc.typeStraipsnis konferencijos darbų leidinyje kitoje DB / Paper in conference publication in other DB
dcterms.references10
dc.type.pubtypeP1c - Straipsnis konferencijos darbų leidinyje kitoje DB / Article in conference proceedings in other DB
dc.contributor.institutionVilniaus Gedimino technikos universitetas
dc.contributor.facultyElektronikos fakultetas / Faculty of Electronics
dc.subject.researchfieldT 001 - Elektros ir elektronikos inžinerija / Electrical and electronic engineering
dcterms.sourcetitleBEC 2010: 12th Biennial Baltic electronics conference : proceedings. Tallinn University of Technology, October 4-6, 2010, Tallinn, Estonia
dc.publisher.nameIEEE
dc.publisher.cityNew York
dc.identifier.elaba3982432


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