SURF algorithm implementation on FPGA

Abstract

This paper describes the hardrvare implementation of the modified speeded-up robust features (SURF) algorithm. Field Programmable Gate Array (FPGA) is selected as a hardware platlbrm for implementation of the modified SURI" algorithm. FPGA base platform is selected to ensure l'eatures extraction in real-tirne video. A sliding windorv buffer is used to store shifted pixels of integral video frame at each clock signal. The bulTer is shared with Hessian determinant, orientation and descriptor units. l'he interest points are searched in 8 scales in parallel by applying the non-maximal suppression. 'fhe tlrientation vector and simplified descriptor is computed for each feature in 6 scales. 'fhe proposed architecture is irnplemented using VHDL and achieves reat-time orientation and descriptor calculation on 60 fps 640x480 video stream only on 25 NlHz clock.