Design of low noise 10 GHz divide by 16…511 frequency divider

Abstract

In this paper design and simulation of a 10 GHz, divide by 16…511 programmable frequency divider based on ETSPC and TSPC logic flip-flops in 65 nm CMOS are presented. Main blocks of the divider are three-stage dual modulus divide by 2/3 divider chain, 6-bit counter, jitter removal and synchronisation flip-flops. Extended True Single Phase Clock (ETSPC) logic is used for 2/3 dividers to achieve high input frequency and low power and TSPC logic is used for 6-bit counter. Simulation of the divider was made using Cadence software. Divider’s operation frequency is up to 10 GHz. Resulted phase noise is -143.7 dBc/Hz at 1 kHz offset from output frequency and power dissipation is 29.35 mW when input frequency is 10 GHz, division ratio is set to 23, supply voltage 1.2 V. The main application of such divider is as feedback divider in frequency synthesizer for wireless communication systems.