The lattice-ladder neuron and its training circuit implementation in FPGA

Abstract

FPGA implementation of a lattice-ladder multilayer perceptron structure together with its training algorithm in a full scale seems attractive, however there is a lack of preliminary results on the choice of implementation architecture. The aim of this investigation was to get insights on the selected neuron model fixed-point architecture (necessary to use word length) and its complexity (required number of LUT and DSP slices and BRAM size) by the evaluation of the reproduced by lattice-ladder neuron accuracy of bandwidth and central frequency as also as output signal normalized mean error. Thus the second order fixed-point normalized lattice-ladder neuron with its training algorithm was implemented in Artix-7 FPGA. The experiments were performed using various bandwidths and word length constrains. In general increase of word length yielded smaller mean errors. However the limited size BRAM used for trigonometric function LUTs was a bottleneck to improve the precision while doubling the number of DSP slices.