Intravenous glucose tolerance test hardware implementation

Abstract

Blood glucose level monitoring and control is of utmost importance to millions of people who have been diagnosed with diabetes or similar illnesses. One of the conventional tests for measuring how the human body breaks down glucose is IVGTT, the Intravenous Glucose Tolerance Test. The difficulty of computing the models of glucose-insulin interaction presents an issue when attempting to implement them in embedded hardware. The Metabolic P (MP), contrary to other models, does not require solving differential equations to compute, thus it could be an effective modelling approach for real-time applications. The present paper proves that MP system methodology-based IVGTT implementation in the Field Programmable Gate Arrays (FPGA) technology is reasonably precise and sufficiently flexible to be used effectively in multi-user scenarios. Presentation of the state-of-the-art focuses on glucose-insulin interaction models, glucose monitoring systems and MP system implementation techniques. Methods for MP system computations and techniques for their implementation on FPGA, together with the original unified MP system implementation technique, have been presented in this paper. The results of an elaborate investigation into the IVGTT MP systems, as well as their single and unified MP implementation techniques have also been considered. It is shown that the techniques developed are applicable to all known IVGTT MP systems, and can achieve RMSE not higher than 15% using a word length of at least 32 bits. The novel MP system combined quality metrics and its pictorial representation allow the analysis of various implementation characteristics. Compared to the unified pipelined IVGTT MP system implementation technique, the developed unified combinational technique ensures a 2‒3 times higher speed.