The evaluation of configurable core for disparity map computation based on FPGA

Abstract

The article presents the evaluation of configurable hard-core for disparity map computation based on FPGA. The proposed hardware architecture performs the computation of disparity map in a pipelined order. The local block matching based on sum of absolute differences is performed for the search of corresponding similarities in two stereo images. The disparity core is implemented on Virtex-4, Artix-7, Kintex-7 FPGAs and the corresponding results on required resources and performance are presented. The core was evaluated under: VGA, HD720 and HD1080 formats of video stream, local block sizes from 4 × 4 to 32 × 32 pixels and maximal disparity ranges from 32 up to 512 pixels. The results show that using xc4vsx35 FPGA the maximal frame rates are 224, 75 and 33 frames per second for VGA, HD720 and HD1080 video formats, respectively.