Investigation of complex algorithm of Digital Signal Processing of High-Speed DACs Signals for Settling Time Testing
Date
2017Author
Kvedaras, Rokas
Kvedaras, Vygaudas
Ustinavičius, Tomas
Masiulionis, Ričardas
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The paper represents the results of the investigation of the complex Digital Signal Processing algorithm for the processing of the measurement signals of the Settling Time Measurement of the Digital-to-Analog Converters. The results of the investigations show that the obtained results ensure suppression of the white noise and 1/f noise by up to 100 times and it is possible to measure settling times of up to 16 bit high-speed DACs with readout levels of ± 0.5 LSB while measurement errors not exceed ± 0.6 ns.