Synchronization of AXI streaming interfaces for convolution core implementation on FPGA

Abstract

The article presents application of DMA controllers in conjunction with ZynQ SoC high performance ports for data streaming to convolution core implemented on programmable logic. The core processes AXI stream directly receiving data on 8 input channels and pushes results from 8 output channels on stream-to-memory-map bus. Two AXI streaming interfaces are synchronized in FPGA direction and second two - in DDR memory direction achieving peak 762 MB/s write and read throughput. The performance of hardware/software co-design of 16 bit CNN is restricted by frequent access to DDR due to core sharing in a time through all layers. Nevertheless, proposed CNN architecture executes 32.8 GOPS running at 50 MHz and it can be applied to solve object detection tasks with tiny nets.