A Low-Power 10-bit 72 MS/s Continuous Successive-Approximation Analog-to-Digital Converter

Abstract

This paper proposess a Low-Power 10-bit 72 MS/s Successive Approximation Analog-to-Digital Converter (SAR ADC), implemented using TSMC 40 nm CMOS technology. The proposed design possesses an innovative dynamic adjustment SAR logic circuit to reduce the conversion power consumption and shorten the conversion time such that smapling rate is up to 72 MS/s. Additionally, a novel high-density and low noise unit capacitor structure is utilized to replace traditional MOM and MIM capacitors. This new capacitor architecture with extremely low unit capacitance could further reduce the power consumption during capacitor switching period. According to the simulation results, the proposed architecture achieves a 10-bit resolution, with a maximum DNL of 0.817 LSB and a maximum INL of 0.895 LSB. The SNDR is simulated to be 58.904 dB and 53.39 dB with the input frequenct at 7.19 MHz and 35.84 MHz, respectively.