Improved MOS Current Mode Logic based Tri-state Buffer using DTMOS and its Applications

Abstract

An improved MOS Current Mode Logic (MCML) tri-state buffer design for low-voltage and low-power applications using Dynamic Threshold Voltage MOSFETs (DTMOS) is presented in this work. By using DTMOS transistors for traditional pull-down transistors, the suggested design lowers the threshold voltage and total supply voltage needs. Due to this development, the circuit can function at a lower supply voltage. With applications shown in bus realization and D-Latch configurations, a comparison analysis between the proposed MCML tri-state buffer and available design is carried out to evaluate the efficacy of the proposed design. Through comprehensive SPICE simulations using 180nm TSMC CMOS technology parameters, the functionality of both designs is confirmed.